This invention relates to an optical packet switch (or switching system) for switching individual packets using an optical switch. More particularly, the invention relates to an optical packet switch in which, without using sophisticated clock synchronizing technology, it is possible to deal with a variation in frame phase due to factors such as skew in an optical switch, thereby making it possible to achieve accurate retiming.
Techniques for constructing large-scale packet switches using optical switches are known in the art. However, it is very difficult to perform routing within the switch by referring to packet headers using optical elements alone and to achieve a packet memory using optical elements. For these reasons, packet switches are constructed by combining optical elements with electric circuits. In such a packet switch, the packet switching function is performed by an optical switch and the input/output units of the optical switch are implemented by electric circuits. In an optical switch of the waveguide type, the optical circuit of an optical directional coupler is formed on a substrate made of a GaAs- or InP-compound semiconductor or of a strongly dielectric material such as LiNb03, and the optical path is switched by changing the state of optical coupling by voltage applied to electrodes provided on two closely adjacent optical waveguides. Such an optical switch is capable of high-speed switching on the nanosecond order, by way of example.
FIGS. 8 to 10 are diagrams each illustrating the general structure of an optical packet switch according to the prior art. Each of these optical packet switches employs input and output interface cards composed of electric circuits and an optical switch constituted by optical elements.
For an understanding of the structures of the devices shown in FIGS. 8 to 10, refer to the specifications of Japanese Patent KOKAI Publications JP-A-10-123577 and JP-A-6-232897, by way of example.
In the optical packet switch shown in FIG. 8, a signal transferred on an optical waveguide 206 selected within an optical switch 205 is a packet-data signal only; no clock signal is transferred. An output interface card 211 has an optoelectronic transducer 208 by which the arriving optical signal transferred through the optical switch 205 is converted to an electric signal, a bit buffer 210 of a transfer terminating circuit 209 in which the electric signal is stored temporarily and read out subsequently as a packet-data signal, and a transmit circuit 219 for outputting a packet-data signal 215 that has thus been retimed.
A problem with the arrangement of this device, however, is how the packet-data signal will be terminated by the clock within the packet of the output interface card 211. Specifically, with the device shown in FIG. 8, a master clock unit 212 within the device distributes a master frame signal 213 to various components in the device (in FIG. 8, to a receive circuit 201 in an input interface card 203 and to the transfer terminating circuit 209 in the output interface card 211). The output interface card 211 performs retiming by generating a clock synchronized to the master frame signal 213 and reading the packet-data signal, which is transferred from the optical switch 205, out of the bit buffer 210 in response to the generated clock.
If the packet-data signal is a high-speed signal whose frequency is on the gigahertz order or greater, the packet-data signal that enters the output interface card 211 via the optical switch 205 will experience a signal delay or skew that differs depending upon which input interface card it has been transferred from, i.e., depending upon the signal path. It is extremely difficult to define and produce an intra-package clock signal that is capable of being received uniformly by the output interface card 211 regardless of the particular skew. As a result, there is no alternative but to adjust timing by a highly precise adjustment within the device.
In the device illustrated in FIG. 9, a burst-receiving PLL (Phase-Locked Loop) circuit 230 regenerates a receive clock signal 217 from the packet-data signal that has been regenerated by the output interface card 211. The burst-receiving PLL circuit 230, the input to which is an output signal of an optoelectronic transducer 208, extracts timing information from the packet data (which is a burst signal) on a packet-by-packet basis and generates the receive clock signal 217 by which the packet-data acceptance timing in the bit buffer 210 is controlled. As a result, the packet-data signal in the output interface card 211 is retimed so that the packets can be accepted.
A problem with the device depicted in FIG. 9 is that, in the first place, implementing the burst-receiving PLL circuit 230 is difficult. It is particularly difficult to construct a burst-receiving PLL circuit that extracts a clock dynamically packet by packet at high speed on the gigahertz order or greater. Even if such as PLL circuit can be realized it would require too much time to extract the clock. As a consequence, it is impossible to extract a clock and accept data while following up packet transfer on the order of several microseconds or less.
The device shown in FIG. 10 seeks to avoid the above-described clock adjustment in the output interface card 211. To accomplish this, wavelengths from a plurality of input interface cards 203 are allocated regularly to all output interface cards 211 and optical signals having these wavelengths are always passed through the optical switch 205. The output interface card 211 electrically terminates the optical signal of each wavelength from each of the input interface cards 203 and extracts the clock. In other words, a signal always flows on a transfer path from a certain input interface card 203 to the output interface card 211, and the output interface card 211 performs constant clock extraction individually from signals that are transferred from all of the plurality of input interface cards 203. This solves the above-mentioned problem associated with dynamic clock extraction and makes it possible to implement arbitrary packet transfer.
Specifically, each output interface card 211 is provided with a receive circuit (DMUX) 230 comprising a plurality of optoelectronic transducers 208 and bit buffers 210 corresponding to respective ones of the plurality of input interface cards (#1 to #N, where N=2 in FIG. 10) 203, and with a selector 220 for selecting any one of the outputs of the DMUX 230. The wavelengths of the optical signals that are transmitted over the optical waveguides 206 of the optical switch 205 differ for each input interface. In comparison with the arrangement shown in FIG. 8, the scale of the electrical receiving circuitry in the output interface card 211 is increased by a factor equivalent to the number (N) of input interface cards, and the scale of the electrical circuitry of the overall device also is increased by a factor of N. This increases the size of the device and raises the cost thereof. In addition, the number of wavelengths of the optical signals transmitted through the optical switch 205 also is N times the number of wavelengths in the arrangements shown in FIGS. 8 and 9. The result is an increase in the size and cost of the optical switch 205.
Thus, the devices according to the prior art give rise to the following problems:
The first problem is that the device shown in FIG. 8 is disadvantageous in that it is difficult for the output interface card 211 to retime packet-data signals that are transferred from different input interface cards. The reason for this is that since signal delay or skew is produced that differs depending upon the input interface cards for different sources of transmission, intra-package clock information capable of being received indiscriminately regardless of the particular skew is difficult to be extracted from the master frame signal.
There is the second problem as follows. With the device shown in FIG. 9, the receive clock signal 217 is regenerated from a packet-data signal 216 by the burst-receiving PLL circuit 230 in the output interface card 211 and the burst-receiving PLL circuit 230 extracts timing information from the packet-data signal 216 packet by packet and generates the clock. The retiming of the packet-data signal 216 is performed by the clock and the packet is accepted. However, difficulty is encountered in the very act of constructing the burst-receiving PLL circuit 230 that extracts the clock dynamically packet by packet at high speeds at an operating frequency on the gigahertz order or greater. Extracting the clock would take too much time even if such a PLL circuit could be constructed, and it would be impossible to extract a clock and accept data while following up packet transfer on the order of several microseconds or less. This is the second problem with the prior art.
There is the third problem as follows. The problem with the device shown in FIG. 10 is that the output interface card 211 is provided with the electrical receiving circuitry for supporting all of the input interface cards 203. In comparison with the arrangements shown in FIGS. 8 and 9, the scale of the electrical receiving circuitry in the output interface card is increased by a factor equivalent to the number (N) of input interface cards and the scale of the electrical circuitry of the overall device also is increased by a factor of N. This results in a much larger device and in higher cost. Furthermore, the number of wavelengths of the optical signals transmitted through the optical switch also is N times the number of wavelengths in the arrangements shown in FIGS. 8 and 9. The result is an increase in the size and cost of the optical switch.
In a packet switch, the relationship between data and retiming clock control information is uniquely determined in each circuit block that resides along the data transfer path within the device. Accordingly, the master clock unit within the device transfers a reference clock to each of the other blocks. By retiming the data in each of the circuit blocks in accordance with a clock phase shifted a fixed length from the reference clock, packets can be sent and received correctly.
However, in a case where an optical switch is used as the switch in the device, as in the devices of the prior art described above, skew within the optical switch gives rise to difficulties. Specifically, whenever an input port for the source of a packet transmission is switched by the switching action of the optical switch, the clock information necessary for retiming of the packet data changes at the output port owing to skew. Consequently, it is impossible to send and receive packets merely by stipulating the unified clock from the master clock unit.
The purpose of a packet switch using an optical switch originally is to realize a high-capacity packet switching performance. Individual transfer speeds are made very high. Skew produced within the optical switch amounts to several bits or more, for example, the result of which is a large fluctuation not only in bit phase (the bit phase undergoes a timing adjustment by retiming) but also in frame phase. This makes retiming of data extremely difficult.
According to Japanese Patent Kokai Publication JP-A-1-238248 (U.S. Pat. No. 2,595,025), there is the following disclosure relating to a high-speed packet switch using an optical switch, a clock signal and packet data are wavelength multiplexed and then transferred using the same path through the optical switch. On the output side of the optical switch the wavelengths are demultiplexed, the packet data and clock are converted to electric signals and the packet data is retimed by being variably delayed and then input to a flip-flop using the clock. As a result, even there is a delay between input and output owing to switching of the optical switch connection, retiming of the packet data is performed at an optimum timing. However, with the technique disclosed in the above-mentioned publication, no consideration is given to skew and to periods of signal instability etc. when the optical switch is switched. As mentioned above, skew produced in the optical switch is several bits or greater. Consequently, it is not possible to solve the problem of large fluctuation not only in bit phase but also in frame phase. As a result, this packet switch is not suitable for practical applications. As aforementioned, there is much to be desired in the optical packet switch (or switching system/method).
Accordingly, an object of the present invention is to provide a packet switch in which electrical circuits are used to implement the input and output sections of an optical switch that performs packet switching, wherein the retiming of packet data in the output section is facilitated and an increase in the scale of the circuitry is suppressed.
Another object of the present invention is to provide an optical switch that makes it possible to perform retiming at high speed regardless of a fluctuation not only in bit phase but also in frame phase caused by skew produced in an optical switch by transfer. Further objects of the present invention will become apparent from the entire disclosure including the claims and drawings.
Generally, the following concept underlies the present invention. In accordance with the present invention, clock information for the purpose of retiming on the output side is transferred, together with a packet-data signal, in the form of an optical signal when the packet-data signal is transferred through an optical switch. The packet data is placed in an intra-device frame, which has a preamble of a predetermined length and dummy data, taking into account skew of the optical switch and a period of signal instability when switching is performed. Intra-device packets and the clock information for retiming are multiplexed and transferred on the same path through the optical switch. On the output side the intra-device packet data and the clock information are demultiplexed from the received signal, the starting position of the packet data in an intra-device packet is sensed, and writing of the data in memory is performed from this point onward, thereby achieving retiming.
Specifically according to an aspect of the present invention, there is provided an optical packet switch having an input unit and an optical switch, wherein the input unit multiplex a control signal with packet data, which is to be transferred to a destination output unit via the optical switch, and sends the multiplexed packet data and control signal to the optical switch, the control signal being for the purpose of retiming the packet data at the destination output unit that receives the packet data;
the input unit generating an intra-device frame signal comprising a format having dummy-bit strings of predetermined lengths, which take into consideration switching timing of the optical switch and skew produced by transfer of the packet data through the optical switch, provided at the beginning and end, respectively, of the frame, and placing the packet data in a data storage area of the intra-device frame signal to thereby transfer the packet data to the destination output unit via the optical switch.
According to a second aspect of the present invention, there is provided an optical packet switch having an input unit and an output unit of an optical switch which performs packet switching, the input and output units each comprising an electric circuit;
where in the input un it has a frame signal generator of an intra-device frame signal having a format comprising a preamble, dummy data and input packet data interposed between the preamble and the dummy data, the preamble and the dummy data having lengths, the intra-device frame signal generator being designed to accommodate a period of signal instability produced when switching is performed by the optical switch as well as skew caused by transferring the packet data through the optical switch, and for append a retiming control signal, which is for controlling retiming of the packet data at the output unit, to the intra-device frame signal and then sending the intra-device frame signal to an optical transmission path of the optical switch; and
wherein the output unit is designed to multiplex optical signals, which have been transferred from the optical switch, into the intra-device frame signal and retiming control signal, retime the demultiplexed intra-device frame signal by the demultiplexed retiming control signal and outputting the packet data extracted from the intra-device frame signal upon handing the intra-device frame signal over to an output clock signal. The output unit may be designed to sense a starting position of the packet data using the retiming control signal, write the packet data, from this starting position to an end position, to a storage device using the demultiplexed timing control signal as a write control signal, and to read the packet data out of the storage device using the output control signal as a read-out signal.
According to a third aspect of the present invention, there is provided an optical packet switch having an input unit, an optical switch which performs packet switching and an output unit thereof, the input and output units each comprising an electric circuit, wherein retiming control information, which is for retiming packet data in the output unit, is transferred in the form of an optical signal from the input unit to the output unit through the optical switch;
the input unit including:
a packet data receiver designed to receive the packet data from a transmission line and generating an intra-device frame by placing the packet data in a data field of an intra-device frame having a frame format comprising a preamble having a length that accommodates skew produced by transfer of the packet data through the optical switch, a flag pattern for sensing starting position of the data field, the data field, and dummy data having a length at least equal to switching time of the optical switch; and
a wavelength multiplexer designed to wavelenght-multiplex a retiming control signal, which is for retiming the packet data in the output unit, with the intra-device frame that has been generated, an d sending the wavelength-multiplexed intra-device frame signal and packet data to an optical transmission path of the optical switch;
the output unit being designed to demultiplex optical signals, which have been transferred from the optical switch, into the intra-device frame signal and retiming control signal, sense starting position of the packet data by sensing the flag pattern in the intra-device frame signal, write the packet data from the starting position to storage means using the separated retiming control signal as sa write control signal, read the packet data out of the storage means based upon a read-out timing control signal, and output the packet data to a transmission line via a transmit circuit.
According to a fourth aspect of the present invention, there is provided an optical packet switch having an input unit, an optical switch which performs packet switching and an output unit thereof, the input and output units each comprising an electric circuit;
the input unit including:
means for receiving data at a transmission-line input and extracting a receive clock signal and a receive packet-data signal;
means for changing over from the receive clock signal to a first clock signal synchronized to a master frame signal that stipulates length of a reference frame period within the optical packet switch, achieving retiming using the first clock signal, and generating an intra-device frame signal having a frame format comprising a preamble and dummy data each of predetermined lengths, with the packet data being interposed between the preamble and the dummy data; and
means for converting the intra-device frame signal and the first clock signal to mutually different optical wavelengths, wavelength multiplexing the wavelength of the intra-device frame signal and the wavelength of the clock signal and transferring the wavelength multiplexed signals to the optical switch;
the optical switch transferring the wavelength of the intra-device frame signal and the wavelength of the first clock signal over an identical path;
the output unit including:
means for demultiplexing the wavelength of the intra-device frame signal and the wavelength of the clock signal transferred from the optical switch, converting these wavelengths to respective ones of electric signals, and outputting the electric signals as an intra-device frame signal and a second clock;
means for receiving the intra-device frame signal by performing retiming using the second clock signal, changing over from the second clock signal to a third clock signal synchronized to the master clock signal, and extracting a packet-data signal from the intra-device frame signal; and
means for outputting the extracted packet data to a transmission line.
The intra-device frame may include, starting from a leading edge thereof, a preamble having enough length to accommodate skew that accompanies transfer of packet data through the optical switch, a flag pattern of a predetermined length, a data field, and dummy data having a length conforming to switching time of the optical switch;
the input unit placing the packet data in the data field to thereby transfer the packet data to the output unit via the optical switch.
According to a fifth aspect of the present invention, there is provided an optical packet switch having an optical switch which performs packet switching, an input unit and an output unit, a master frame signal, which specifies length of a reference frame period within the optical packet switch, being input to the optical switch, the input unit and the output unit, the optical switch switching a connection between the input and output units based upon the master frame signal;
(a) the input unit including:
(a1) means for extracting packet data from a signal input from a transmission line, bit synchronizing the packet data to a first clock signal generated using the master frame signal as a reference, and generating a fixed-length intra-device frame signal having a frame format comprising a preamble having enough length to accommodate signal skew that is caused by transfer of the signal through the optical switch, a flag pattern for sensing starting position of a data field, a data field containing the packet data, and dummy data having a length at least equal to switching time of the optical switch; and
(a2) wavelength multiplexing means for wavelength multiplexing a wavelength of an intra-device frame signal and a wavelength of a clock signal obtained by converting the first-mentioned intra-device frame signal and the first clock, respectively, to optical signals having mutually different wavelengths, and sending the optical signals of the multiplexed wavelengths to the optical switch;
(b) the output unit including:
(b1) means for wavelength demultiplexing, by wavelength demultiplexing means, the optical signals constituted by the wavelength-multiplexed wavelength of the intra-device frame signal and wavelength of the clock signal transmitted through the optical switch, converting these two demultiplexed optical signals to electric signals and outputting them as an intra-device frame signal and a second clock signal, respectively;
(b2) means for sensing starting position of the data field by sensing the flag pattern in the intra-device frame signal, and performing control in such a manner that the packet data contained in the data field is written to a storage device in sync with the demultiplexed second clock signal; and
(b3) means for reading the packet data out of the storage means in response to a third clock synchronized to the master frame signal and outputting the packet data to a transmit circuit in order to output the packet data to a transmission line.
According to a sixth aspect of the present invention, there is provided an optical packet switch having an optical switch which performs packet switching, an input unit and an output unit, a master frame signal, which specifies length of a reference frame period within the optical packet switch, being output from master frame generating means and input to the optical switch, the input unit and the output unit, the optical switch switching a connection between the input and output units based upon the master frame signal;
(a) the input unit including:
(a1) an input signal receiver designed to for receive an input signal from a transmission line, extracting packet data in a payload of a frame, to bit-synchronize the extracted payload data to a first clock signal generated using the master frame signal as a reference, to generate and output an intra-device frame signal having a preamble having a predetermined length, a flag pattern, a data field following the flag pattern and containing the packet data, and a dummy pattern, and to output the first clock signal;
(a2) first and second electro-optic transducers converting the intra-device frame signal and the first clock signal, which are input thereto, to an optical signal having a wavelength of an intra-device frame signal and an optical signal having a wavelength of a clock signal, and outputting the optical signals, the wavelengths being different from each other; and
(a3) a wavelength multiplexer, to which are input the wavelength of the intra-device frame signal and the wavelength of the clock signal constituting the optical signals output from respective ones of the first and second electro-optic transducers, designed to wavelenght-multiplex these wavelengths and output them to the optical switch;
(b) the output unit including:
(b1) a wavelength demultiplexer, to which the optical signals from an optical transmission path of the optical switch are input, for wavelength demultiplexing these optical signals to the wavelength of the intra-device frame signal and the wavelength of the clock signal;
(b2) first and second optoelectronic transducers, to which the wavelength of the intra-device frame signal and the wavelength of the clock signal demultiplexed and output by the wavelength demultiplexer are respectively input, for converting the same to an electric intra-device frame signal and an electric second clock signal, respectively;
(b3) an intra-device frame terminator having:
(b3-1) means for receiving the intra-device frame signal and the second clock signal respectively output from the first and second optoelectronic transducers, and sensing starting position of the data field by sensing a match with the flag pattern from the intra-device frame in sync with the second clock signal;
(b3-2) means for performing control in such a manner that when the starting position of the data field is sensed from the intra-device frame signal, the packet data from the starting position of the data field to an end position thereof is written to a memory in sync with the second clock signal, the second clock signal serving as a write signal; and
(b3-3) means for reading the packet data out of the memory in sync with a third clock generated using the master frame signal as a reference, the third clock serving as a read-out signal; and
(c) transmit means for transmitting the packet data from the intra-device frame terminator.
The intra-device frame terminator may include:
flag pattern sensing means for sensing the flag pattern of the intra-device frame signal;
memory means for storing the pattern data temporarily;
write control means, responsive to a signal from the flag pattern sensing means indicating that the flag pattern has been sensed, for applying a write-enable signal to the memory means, wherein the packet data in the data field following the flag pattern in the intra-device frame signal is written to the memory means in sync with the second clock signal;
read-out control means, responsive to a read-out start signal output from the write control means after a predetermined number of bits have been written to the memory means, for applying a read-out-enable signal to the memory means, whereby timing of start of read-out from the memory means is control led so that read-out is performed a predetermined number of bits after writing of the packet data to the memory means has started;
the packet data being read of the memory means in sync with the third clock signal;
clock synchronizing means, to which the master frame signal is input, for generating the third clock in sync with the master frame signal; and
phase control means for controlling operation start timing of the flag-pattern sensing means, the write control means and the read-out control means based upon the third clock signal from the clock synchronizing means.
The phase control means may receive the third clock signal, outputs first and second operation start signals, which are for enabling start of operation of the flag-pattern sensing means and write control means, respectively, at predetermined timings before start of the flag pattern and start of data field, respectively, of the intra-device frame signal, and output a third operation start signal, which is for enabling start of operation of the read-out control means, at a predetermined timing after output of the first and second operation start signals but before start of the data field.
The write control means deactivates the write-enable signal, which is supplied to the memory means, during the interval of the dummy data in the intra-device frame signal.
In a further aspect of the present invention, the optical packet switch comprises a plurality of the input units, a plurality of the output units, the optical switch, packet scheduler means and master clock generating means;
each of the input units first sending a request signal to the packet scheduler means when packet data is transferred to a destination output unit through the optical switch;
the packet scheduler means deciding, on the basis of the request signal from each input unit, an input unit and an output unit that are allowed to perform a transfer, sending an enable signal to the input unit that has been allowed to perform a transfer, sending an enable signal to the output unit that has been allowed to perform a transfer, and sending a switch setting signal to the optical switch;
the packet switch connecting an optical waveguide between the decided input unit and the output unit by the switch setting signal from the packet scheduler means; and
the master clock generating means supplying the input unit, the output unit and the packet scheduler means a master clock signal for specifying a frame period.
In a preferred embodiment of the present invention, an optical packet switch uses electric circuits to implement input and output sections of an optical switch that performs packet switching, wherein retiming control information, which is for retiming packet data in the output section, is transferred together with the packet-data signal in the form of an optical signal from the input section to the output section over the same path through the optical switch.
The clock signal constituting the retiming control information for achieving retiming in the output section preferably is wavelength multiplexed with the packet-data signal and transferred over the selected path through the optical switch. As a result, it is possible to minimize a difference in delay between the two signals. The packet-data signal is retimed in the output section based upon the clock information that has been transferred through the optical switch.
In a preferred embodiment of the present invent ion, the optical packet switch includes an input section of an optical switch, the input section having means for generating an intra-device frame signal having a frame format composed of a preamble, which has a predetermined length greater than skew caused by transferring input packet data through an optical switch and a period of signal instability produced when switching is performed by the optical switch, a flag pattern following the preamble, dummy data at the end and the packet data interposed between the flag pattern and the dummy data. A retiming control signal for retiming the packet data in the output section is multiplexed onto the generated intra-device frame signal and transmitted on the same optical transmission path through the optical switch.
In a preferred embodiment of the present invention, the output section of the optical packet switch demultiplexes (i.e., separates) the intra-device frame signal and retiming control signal from the optical signals that have been transferred from the optical switch, senses the starting position of the packet data with regard to the intra-device frame signal, writes the packet data to storage means (memory) from this starting position using the demultiplexed retiming control signal as a write control signal, reads the packet data out of the storage means based upon a read-out timing control signal and outputs the packet data over a transmit circuit.
In the present invention, an intra-device frame (see FIG. 5) for packet transfer through the optical switch is newly defined to simplify packet processing in the output section after retiming of the packet-data signal and to assure the timing precision of the retiming operation. The intra-device frame signal is newly defined for the purpose of transfer through the input section, optical switch and output section and the length thereof is decided by the master frame signal, which determines the length of the reference frame period within the optical packet switch. The intra-device frame signal comprises a preamble, a flag pattern, a data field and dummy data.
The preamble at the beginning of the intra-device frame is designed to have a length that takes into account the period of signal instability produced at switching of the optical switch as well as maximum skew produced by transfer through the optical switch. The dummy data at the tail end of the frame is decided taking into consideration the switching time of the optical switch or the difference between write and read timings of a bit buffer designed to retime. The flag pattern is for sensing the starting position of the data field. The latter contains the packet data. In the input section the intra-device frame signal is bit-synchronized to the lock signal produced using the master frame signal as a reference, and the intra-device frame signal is transferred to the output section, together with the clock signal, through the optical switch. The packet data is extracted and then transmitted to the transmission line upon being retimed in the output section.
In accordance with the present invention constructed as set forth above, it is possible to construct an optical packet switch, which uses an optical switch, that achieves packet transfer at a speed much higher in comparison with the prior art. It is unnecessary for the output section to be provided with a circuit for generating clock information in dependence upon packet data transferred to the output section. Furthermore, in regard to working the present invention, the optical switch need not be provided with additional functions; it is possible for an existing optical switch to be used as is.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.